With the growing size of real-world datasets running on CPUs, address translation has become a significant performance bottleneck.
In this paper, we propose CoPTA, a technique to speculate the memory address translation upon a TLB miss to hide the page table walk latency. Specifically, we show that the operating system has a tendency to map contiguous virtual memory pages to contiguous physical pages. Based on this observation, we devise a speculation mechanism that finds nearby entries present in the TLB upon a miss and predicts the address translation of the missed address assuming contiguous address allocation. This allows CoPTA to speculatively execute instructions without waiting for the PTW to complete. We run the PTW in parallel, compare the speculated and the translated physical addresses, and flush the pipeline upon a wrong speculation with similar techniques used for handling branch mispredictions.